JOINT PLENARY SPEAKERS
Executive Vice President
Digital & Smart Power Technology and Digital Front-End Manufacturing
Artificial Intelligence: Why Moving it to the Edge?
This keynote is describing the evolution of Artificial Intelligence (AI) adoption to the Edge for maximizing Data processing at the User experience level to treat as much as possible data analysis without saturating Internet traffic and Cloud data centers. Evolution of Neural Network (NN) computing through progressive usage of In Memory Computing (IMC) is also described. A few examples of Artificial Intelligence at the Edge are also commented. We then describe how at ST, we address competitive solutions for Edge AI thanks to differentiated FD-SOI CMOS technology, Phase Change Memory (PCM) embedded memory integration and advanced NN and IMC design solutions.
Joël Hartmann is Executive Vice President of STMicroelectronics, Digital & Smart Power Technology and Digital Front-End Manufacturing, and has held this position since February 2012. He manages ST’s manufacturing operations in Crolles and Rousset, France, Technology and Design Platforms for the Company’s digital products. In December 2018, Hartmann’s mandate was expanded with ST’s Smart Power Technology R&D operations in Agrate, Italy. From 1979 to 2000, Hartmann worked at CEA-Leti, France-based applied-research center. In 2000, he joined STMicroelectronics as Director of the Crolles2 Alliance, the semiconductor manufacturing R&D initiative of STMicroelectronics, NXP, and Freescale Semiconductor. In 2008, Hartmann was promoted to Group Vice President and Director of Advanced CMOS Logic & Derivative Technologies. From 2010 to 2012, he had additional responsibilities as a co-leader of the Semiconductor Research and Development Center in Fishkill, NY, within the IBM ISDA Technology Alliance for advanced CMOS process development. Hartmann is a Member of the IEEE Electron Device Society. In 2017, he became a member of the French “Académie des Technologies” and received the European SEMI Award in 2019. Hartmann has filed 15 patents on semiconductor technology and devices and authored 10 publications in this field to date. Joël Hartmann was born in Toulon, France, in 1955. He graduated from the Ecole Nationale Supérieure de Physique de Grenoble with a degree in Physics.
Deputy Director, Chief Technology Officer
Overcoming the Data Deluge Challenges with Greener Electronics
The purpose of this paper is to propose scientific and technical directions to reach global data and power sobriety while preserving computational efficiency. We present nine opportunities to lower the power consumption of computing units. A growth factor of 100 to 1000 in energy efficiency is achievable in the next 10 years if we take full advantage of all the potential improvements, working simultaneously at all five levels of the technological ecosystem (process steps, circuits, architecture, software and algorithms).
Jean-René Lèquepeys was named CEA-Leti's Vice-President and Director of Programs in January 2019, following more than 30 years of scientific and managerial leadership at both CEA and CEA-Leti. He joined CEA in 1985 in the detection and intrusion-detection laboratory in CEA's central security department and was promoted to lab manager in 1987. He joined CEA-Leti in 1993 as an R&D engineer specializing in image processing and also worked on the institute's telecom projects. He was named head of deployment of the Telecom, Communicating Objects and Smart Card programs in 1999 and was promoted to head of the Circuit Design Department of CEA-Leti in 2005. In that role, Jean-René created a research center in Gardanne (France), pioneering secured electronic components, in partnership with School of Mines of Saint-Etienne (France). In 2010, he started a new department specializing in electronic architectures, integrated circuit design and embedded software, bringing together CEA-Leti and CEA-List researchers. He also helped launch CEA-Leti's Silicon Components Division in 2011 and was named head of the division in 2017. Jean-René returned to the Electronic Architectures, Integrated Circuit Design and Embedded Software Department in 2018 before taking his current position.
Jean-René graduated from Supélec (1983) and taught physics for two years in Ouarzazate, Morocco. In 2000, he won the "Grand Prix de l'électronique Général Ferrié" for his work in telecommunications. He holds approximately 15 patents in that field.
Jan M. Rabaey
Professor Emeritus, Professor in the Graduate School
Electrical Engineering and Computer Sciences
University of California, Berkeley, USA
Architecting the Human Intranet
Equipping us humans with the necessary tools to interact with, survive, and prosper in a rapidly changing world may require us to intimately adopt some of the same technologies that are causing some of these changes. Various wearable devices have been or are being developed to do just that. To be effective, functionality cannot be centralized and needs to be distributed to capture the right information at the right place. This requires a human intranet, a platform that allows multiple distributed input/output and information processing functions to coalesce and form a single application. How to effectively do so in light of the many challenges from an efficiency, usability, and effectiveness perspective is the focus of this paper.
Jan M. Rabaey holds the Donald O. Pederson Distinguished Professorship at the University of California at Berkeley. He is a founding director of the Berkeley Wireless Research Center (BWRC) and the Berkeley Ubiquitous SwarmLab, and has been the the Electrical Engineering Division Chair at Berkeley twice.
Prof. Rabaey has made high-impact contributions to a number of fields, including advanced wireless systems, low power integrated circuits, sensor networks, and ubiquitous computing. His current interests include the conception of the next-generation integrated wireless systems over a broad range of applications, as well as exploring the interaction between the cyber and the biological world.
He is the recipient of major awards, amongst which the IEEE Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, and the Semiconductor Industry Association (SIA) University Researcher Award. He is an IEEE Fellow, a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has received honoray doctorates from Lund (Sweden), Antwerp (Belgium) and Tampere (Finland). He has been involved in a broad variety of start-up ventures.
ESSDERC KEYNOTE SPEAKERS
Head of Image Sensor Group
The Essential Contribution of CMOS Imaging Technologies to Earth Observation Applications
In this paper we discuss how the high performances CMOS imaging process improvements, strongly driven by consumer market’s needs, has allowed this technologies to pop-up in the field of Earth Observation instruments traditionally making use of dedicated Charge Coupled Devices (CCD). After reviewing the various Earth image captures techniques and related sensor architectures, the specific requirements on the sensor process will be examined and it will be shown how modern CMOS imaging process, although developed initially for high volume small pixel pitch application, can efficiently fulfill these needs, even allow new performances level, and thanks to additional features enable new achievements particularly suited to the New Space context.
Pierre Magnan graduated in E.E. from University of Paris in 1980. After being a research scientist involved in analog and digital CMOS design up to from 1984 to 1993 in LAAS-CNRS, he moved in 1995 to image sensors research in SUPAERO, now called ISAE-SUPAERO, in Toulouse, France, where he was involved in active-pixels sensors research and development activities. Since 2002, he is Full Professor there and Head of Image Sensor Research Group involved in CMOS Image Sensor research in cooperation with European companies (including STMicroelectronics, Airbus Defense & Space, Thales Alenia Space and also European and French Space Agencies) and development of custom image sensor dedicated to space instruments.
He has supervised 20 PhDs candidates in the field of image sensors and co-authored more than 80 scientific papers. He has served in IEEE IEDM Display Sensors and MEMS subcommittee in 2011, 2012, and in the International Image Sensor Workshop (IISW) TPC in 2007, 2009, 2011, 2017, 2019 and 2021, being the General Technical Chair of 2015 IISW. He has been Associate Guest Editor of the IEEE TRANS. ELECTRON DEVICES for the Special Issue on Solid-State Image Sensors in 2009 and 2015.
His research interests include solid-state image sensors design, modeling, technology, hardening techniques and circuit design for imaging applications.
Doluca Family Endowed Chair and Professor
Electrical and Computer Engineering Department
University of California Santa Barbara, USA
Transistors for 100-300GHz Wireless
We examine the potential design and performance of 100-300 GHz wireless communications systems, examine the required transistors performance, and describe our present efforts to develop InP bipolar and field-effect transistors to serve in the transmitters and receivers of such systems.
Mark Rodwell holds the Doluca Family Endowed Chair in Electrical and Computer Engineering at UCSB and directs the SRC/DARPA ComSenTer Wireless Research Center. His research group develops high-frequency transistors, ICs and communications systems. He and his collaborators received the 2010 IEEE Sarnoff Award, the 2012 Marconi Prize Paper Award, the 1997 IEEE Microwave Prize, the 2009 IEEE IPRM Conference Award, and the 1998 European Microwave Conference Microwave Prize.
School of Electrical and Computer Engineering,
Georgia Institute of Technology, USA
Compute-in-Memory: from Device Innovation to 3D System Integration
Compute-in-memory (CIM) hardware accelerator has been emerged as a promising paradigm for executing the artificial intelligence (AI) tasks owing to its superior energy efficiency. In this keynote presentation, we survey recent progresses of CIM technologies from device-level demonstration to system-level benchmark. First, the ferroelectric devices (FeM-FinFET, ferroelectric non-volatile capacitor) are introduced for resistive and capacitive read-out mechanism for crossbar arrays. Second, resistive random access memory (RRAM) based CIM macro has been taped-out into prototype chips in commercial foundry process and the related NeuroSim validation with measured silicon data is shown. Last, heterogeneous 3D integration scheme for SRAM, RRAM and 3D NAND tiers and logic tier is proposed.
Shimeng Yu is currently an associate professor of electrical and computer engineering at Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University.
Prof. Yu’s research interests are the semiconductor devices and integrated circuits for energy-efficient computing systems. His research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, 3D integration, and hardware security.
Among Prof. Yu’s honors, he was a recipient of NSF Faculty Early CAREER Award in 2016, IEEE Electron Devices Society (EDS) Early Career Award in 2017, ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020, and IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2021-2022, etc.
Prof. Yu served or is serving many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology, IEEE International Reliability Physics Symposium (IRPS), ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc. He is a senior member of the IEEE.